1. Field of Invention
The present invention relates to semiconductor memory and more specifically to non-volatile memory.
2. Description of Related Art
Data is stored as electrons in floating gates of non-volatile memory cells. In high density, low voltage and high-speed applications, a metal-oxide-nitride-oxide-semiconductor (MONOS) can be used where the floating gates are in the form of an oxide-nitride-oxide (ONO) composite layer located under a control gate. There are two separate and independently programmable ONO layers under a single control gate that provides a memory density improvement, as discussed in U.S. Pat. No. 6,549,463 (Ogura et al.). Electrons are stored separately under separate control in the two ONO layers so that two independent memory sites are located under a single control gate. This leads to an increase in storage density.
U.S. Pat. No. 6,248,633 (Ogura et al) is directed to the device structure and operation of a twin MONOS flash memory. In U.S. Pat. No. 6,075,727 (Morton et al.) a method is directed to writing and verifying bits in a non-volatile memory using a three-transistor memory cell. Data in a write latch is compared to data in a cell to determine if the cell has been programmed or erased. U.S. Pat. No. 6,031,760 (Sakui et al.) is directed to a non-volatile semiconductor memory, which includes sense amplifier circuits, each having a latch connected to the sense node. The sense amplifier contains first and second data-latching transistors that are used in a program and verify operation. U.S. Pat. No. 6,009,015 (Sugiyama) is directed to a program verify circuit for a nonvolatile memory array with multi-level stored data. The program verify circuitry contains a latch circuit connected between a bit line and a source/drain of a variable threshold transistor.
The prior art circuits described above are suitable for NAND flash applications in which all memory cells connected to a word line should be programmed at the same time. This simultaneous program is needed because the WL voltage during program is raised to a high voltage, e.g. 20V, creating a very high program disturb condition should there be any unselected cells. Thus, in a NAND flash, since every BL (or every other BL) requires a sense amplifier/verify circuit, the layout is a difficult space challenge, and the circuits must be small and simple.
A Twin MONOS cell and as well as additional kinds of split gate memory cells use the WL as a select gate, which does not require high voltage. So it is possible to selectively decode 1 in 2, 4, 8, etc cells such that several bit lines will share a single sense amplifier/data/verify circuit. Small area size is still important, but additional functionality can be easily included. Also, the sensing circuit itself can be made more sensitive so that sensing time can be reduced.